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AS4DDR232M64PBGR-5/IT 参数 Datasheet PDF下载

AS4DDR232M64PBGR-5/IT图片预览
型号: AS4DDR232M64PBGR-5/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx64 DDR2 SDRAM集成塑封微电路 [32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 363 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
EXTENDED MODE REGISTER (EMR)  
until it is programmed again or the device loses power.  
Reprogramming the EMR will not alter the contents of the  
memory array, provided it is performed correctly.  
The extended mode register controls functions beyond  
those controlled by the mode register; these additional  
functions are DLL enableꢀdisable, output drive strength, on  
die termination (ODT) (RTT), posted AL, off-chip driver  
impedance calibration (OꢁD), DQS# enableꢀdisable,  
RDQSꢀRDQS# enableꢀdisable, and output disableꢀenable.  
These functions are controlled via the bits shown in Figure  
7. The EMR is programmed via the LOAD MODE (LM)  
command and will retain the stored information  
The EMR must be loaded when all banks are idle and no bursts  
are in progress, and the controller must wait the specified time  
tMRD before initiating any subsequent operation. Violating either  
of these requirements could esult in unspecified operation.  
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION  
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
Address Bus  
Extended Mode  
Register (Ex)  
15 14 13 12 11 10  
9
8
7
6
Rtt  
5
4
3
2
1
0
02 out  
OCD Program  
Posted CAS# Rtt ODS DLL  
MRS  
RDQS DQS#  
Outputs  
Enabled  
Disabled  
E0  
DLL Enable  
Enable (Normal)  
Disable (Test/Debug)  
E12  
0
0
1
Rtt (nominal)  
Rtt Disabled  
75Ω  
E6 E2  
1
0
0
1
1
0
1
0
1
Output Drive Strength  
RDQS Enable  
150Ω  
E11  
0
E1  
0
No  
50Ω  
Full Strength (18 Ω target)  
1
Yes  
1
Reduced Strength (40 Ω target)  
E10  
0
DQS# Enable  
Posted CAS# Additive Laten cy (AL)  
E5 E4 E3  
Enable  
Disable  
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
E9 E8 E7  
OCD Operation  
3
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD Not Supported  
Reserved  
4
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1
OCD default state  
Mode Register Set  
Mode Register Set (MRS)  
Extended Mode Register (EMR S)  
E15 E14  
0
1
0
1
0
0
1
1
Extended Mode Register (EMR S2)  
Extended Mode Register (EMR S3)  
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,  
then must be set to "0" before initialization is finished, as detailed in the  
initialization procedure.  
2.. E13 (A13) is not used on this device.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
11  
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