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AS4DDR232M64PBGR-5/IT 参数 Datasheet PDF下载

AS4DDR232M64PBGR-5/IT图片预览
型号: AS4DDR232M64PBGR-5/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx64 DDR2 SDRAM集成塑封微电路 [32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 363 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
MODE REGISTER (MR)  
FIGURE 5 – MODE REGISTER (MR) DEFINITION  
The mode register is used to define the specific mode of  
operation of the DDR2 SDRAM. This definition includes the  
selection of a burst length, burst type, ꢁL, operating mode,  
DLL RESET, write recovery, and power-down mode, as  
shown in Figure 5. ꢁontents of the mode register can be  
altered by re-executing the LOAD MODE (LM) command. If  
the user chooses to modify only a subset of the MR variables,  
all variables (M0–M14) must be programmed when the  
command is issued.  
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
Address Bus  
15  
MR  
14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)  
01 PD  
WR  
DLL TM CAS# Latency BT Burst Length  
Mode  
Normal  
Test  
M7  
0
M2 M1 M0  
Burst Length  
Reserved  
Reserved  
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode  
Fast Exit  
M12  
0
The mode register is programmed via the LM command  
(bits BA1–BA0 = 0, 0) and other bits (M12–M0) will retain the  
stored information until it is programmed again or the device  
loses power (except for bit M8, which is selfclearing).  
Reprogramming the mode register will not alter the contents  
of the memory array, provided it is performed correctly.  
DLL Reset  
No  
M8  
0
(Normal)  
8
1
Slow Exit  
Reserved  
Reserved  
Reserved  
Reserved  
1
Yes  
(Low Power)  
WRITE RECOVERY  
M11 M10 M9  
Reserved  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
Burst Type  
Sequential  
Interleaved  
M3  
0
3
The LM command can only be issued (or reissued) when all  
banks are in the precharged state (idle state) and no bursts  
are in progress. The controller must wait the specified time  
tMRD before initiating any subsequent operations such as  
an AꢁTIVE command. Violating either of these requirements  
will result in unspecified operation.  
4
1
5
6
CAS Latency (CL)  
M6 M5 M4  
Reserved  
Reserved  
Reserved  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
Reserved  
Mode Register Definition  
Mode Register (MR)  
M15 M14  
3
0
1
0
1
0
0
1
1
BURST LENGTH  
4
Extended Mode Register (EMR)  
Extended Mode Register (EMR2)  
Extended Mode Register (EMR3)  
5
6
Burst length is defined by bits M0–M3, as shown in Figure  
5. Read and write accesses to the DDR2 SDRAM are burst-  
oriented, with the burst length being programmable to either  
four or eight. The burst length dete rmines the maximum  
number of column locations that can be accessed for a given  
READ or WRITE command.  
Reserved  
Note: 1. Not used on this part  
BURST TYPE  
Accesses within a given burst may be programmed to be  
either sequential or interleaved. The burst type is selected  
via bit M3, as shown in Figure 5. The ordering of accesses  
within a burst is determined by the burst length, the burst  
type, and the starting column address, as shown in Table  
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst  
mode only. For 8-bit burst mode, full interleave address  
ordering is supported; however, sequential address ordering  
is nibble-based.  
When a READ or WRITE command is issued, a block of  
columns equal to the burst length is effectively selected. All  
accesses for that burst take place within this block, meaning  
that the burst will wrap within the block if a boundary is  
reached. The block is uniquely selected by A2–Ai when BL =  
4 and by A3–Ai when BL = 8 (where Ai is the most significant  
column address bit for a given configuration). The remaining  
(least significant) address bit(s) is (are) used to select the  
starting location within the block. The programmed burst  
length applies to both READ and WRITE bursts.  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
8
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