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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
 浏览型号MEGA128CAN的Datasheet PDF文件第50页浏览型号MEGA128CAN的Datasheet PDF文件第51页浏览型号MEGA128CAN的Datasheet PDF文件第52页浏览型号MEGA128CAN的Datasheet PDF文件第53页浏览型号MEGA128CAN的Datasheet PDF文件第55页浏览型号MEGA128CAN的Datasheet PDF文件第56页浏览型号MEGA128CAN的Datasheet PDF文件第57页浏览型号MEGA128CAN的Datasheet PDF文件第58页  
Watchdog Timer Control  
Register – WDTCR  
Bit  
7
6
5
4
WDCE  
R/W  
0
3
WDE  
R/W  
0
2
WDP2  
R/W  
0
1
WDP1  
R/W  
0
0
WDP0  
R/W  
0
WDTCR  
Read/Write  
Initial Value  
R
0
R
0
R
0
• Bits 7..5 – Reserved Bits  
These bits are reserved bits for future use.  
• Bit 4 – WDCE: Watchdog Change Enable  
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog  
will not be disabled. Once written to one, hardware will clear this bit after four clock  
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This  
bit must also be set when changing the prescaler bits. See “Timed Sequences for  
Changing the Configuration of the Watchdog Timer” on page 55  
• Bit 3 – WDE: Watchdog Enable  
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is  
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared  
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-  
ing procedure must be followed:  
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be  
written to WDE even though it is set to one before the disable operation starts.  
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the  
Watchdog.  
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-  
rithm described above. See “Timed Sequences for Changing the Configuration of the  
Watchdog Timer” on page 55  
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0  
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the  
Watchdog Timer is enabled. The different prescaling values and their corresponding  
Timeout Periods are shown in Table 24.  
Table 24. Watchdog Timer Prescale Select  
Number of WDT  
Oscillator Cycles  
Typical Time-out  
at VCC = 3.0V  
Typical Time-out  
at VCC = 5.0V  
WDP2 WDP1 WDP0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16K cycles  
32K cycles  
17.1 ms  
34.3 ms  
68.5 ms  
0.14 s  
0.27 s  
0.55 s  
1.1 s  
16.3 ms  
32.5 ms  
65 ms  
0.13 s  
0.26 s  
0.52 s  
1.0 s  
64K cycles  
128K cycles  
256K cycles  
512K cycles  
1,024K cycles  
2,048K cycles  
2.2 s  
2.1 s  
54  
AT90CAN128  
4250E–CAN–12/04  
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