Until the conversion is not achieved, it is not possible to start a conversion on another channel.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown Figure 21-15 for AT90PWM2/3.
Figure 21-15. Amplifier synchronization timing diagram for AT90PWM2/3.
Delta V
4th stable sample
Signal to be
measured
PSC
Block
PSCn_ASY
AMPLI_clk
(Sync Clock)
CK ADC
Amplifier
Block
Amplifier Sample
Enable
Amplifier Hold
Value
Valid sample
ADASCR
ADSC
ADC
ADC
Sampling
ADC Result Ready
It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-
sion is started at the next amplifier clock event following the last auto trigger event selected
thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running
mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.
Only PSC sources can auto trigger the amplified conversion. In this case, the core must have a
clock synchronous with the PSC. If the PSC uses the PLL clock, the core must use the PLL/4
clock source.
AT90PWM2B/3B:
On PWM2B/3B, the amplifier has been improved in order to speed-up the conversion time.The
proposed improvement takes advantage of the amplifier characteristics to ensure a conversion
in less time.
In order to have a better understanding of the functioning of the amplifier synchronization, a tim-
ing diagram example is shown Figure for AT90PWM2B/3B.
252
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
