Table 21-7. ADC Auto Trigger Source Selection for amplified conversions
ADTS3
ADTS2
ADTS1
ADTS0
Description
PSC2ASY Event(1)
Reserved
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
1.
For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source.
21.8.4
ADC Result Data Registers – ADCH and ADCL
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
21.8.4.1
21.8.4.2
21.8.5
ADLAR = 0
Bit
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ADC9
ADC8
ADCH
ADCL
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
ADLAR = 1
Bit
7
6
5
4
3
2
1
0
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADCL
ADC1
ADC0
-
-
-
-
-
-
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
Digital Input Disable Register 0 – DIDR0
Bit
7
6
5
4
3
2
1
0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ACMPM
ADC2D
ACMP2D
ADC1D
ADC0D
DIDR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable
250
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
