AT90USB64/128
DPADD10:8 is the most significant part of DPADD. The least significant part is provided by the
UDPADDL register.
Bit
7
0
6
0
5
0
4
3
2
0
1
0
0
0
DPADD7:0
UDPADDL
Read/Write
Initial Value
0
0
• 7-0 – DPADD7:0: DPRAM Address Low Bit
DAPDD7:0 is the least significant part of DPADD. The most significant part is provided by the
UDPADDH register.
Bit
7
-
6
-
5
HNPREQ
R/W
4
SRPREQ
R/W
3
SRPSEL
R/W
2
VBUSHWC
R/W
1
VBUSREQ
R/W
0
VBUSRQC
R/W
OTGCON
Read/Write
Initial Value
R
0
R
0
0
0
0
0
0
0
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – HNPREQ: HNP Request Bit
Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP
when the controller is in the Host mode (A).
Clear otherwise.
• 4 – SRPREQ: SRP Request Bit
Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the
controller is initiating a SRP.
• 3 – SRPSEL: SRP Selection Bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
• 2 – VBUSHWC: VBus Hardware Control Bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
See for more details
• 1 – VBUSREQ: VBUS Request Bit
Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
• 0 – VBUSRQC: VBUS Request Clear Bit
265
7593A–AVR–02/06
ATMEL [ ATMEL ]
