AT89C5132
MMCON2 (S:E6h) – MMC Control Register 2
7
6
5
4
-
3
-
2
1
0
MMCEN
DCR
CCR
DATD1
DATD0
FLOWC
Bit
Number
Bit
Mnemonic Description
MMC Clock Enable Bit
7
MMCEN
Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
6
5
DCR
CCR
-
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
Reserved
The values read from these Bits are always 0. Do not set these Bits.
4 - 3
Data Transmission Delay Bits
Used to delay the data transmission after a response from 3 MMC clock periods
(all Bits cleared) to 9 MMC clock periods (all Bits set) by step of 2 MMC clock
periods.
2 - 1
DATD1:0
FLOWC
MMC Flow Control Bit
Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
0
Reset Value = 0000 0000b
Table 81. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
7
-
6
-
5
4
3
2
1
0
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
Bit
Number
Bit
Mnemonic Description
Reserved
7 - 6
-
The values read from these Bits are always 0. Do not set these Bits.
Card Busy Flag
Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
5
CBUSY
99
4173E–USB–09/07
ATMEL [ ATMEL ]
