AT89C5132
Table 85. MMDAT Register
MMDAT (S:DCh) – MMC Data Register
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit
Number
Bit
Mnemonic Description
MMC Data Byte
7 - 0
MD7:0
Input (write) or output (read) register of the data FIFO.
Reset Value = 1111 1111b
Table 86. MMCLK Register
MMCLK (S:EDh) – MMC Clock Divider Register
7
6
5
4
3
2
1
0
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Bit
Number
Bit
Mnemonic Description
MMC Clock Divider
8-bit divider for MMC clock generation.
7 - 0
MMCD7:0
Reset Value = 0000 0000b
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4173E–USB–09/07