AT89C5132
The interrupt request is generated each time an unmasked flag is set, and the global MMC con-
troller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment). This
implies that register content must be saved and tested interrupt flag by interrupt flag to be sure
not to overlook any interrupts.
Figure 16-20. MMC Controller Interrupt System
MCBI
MMINT.7
MCBM
MMMSK.7
EORI
MMINT.6
EORM
MMMSK.6
EOCI
MMINT.5
EOCM
MMMSK.5
EOFI
MMINT.4
MMC Interface
Interrupt Request
EOFM
MMMSK.4
F2FI
MMINT.3
EMMC
IEN1.0
F2FM
MMMSK.3
F1FI
MMINT.2
F1FM
MMMSK.2
F2EI
MMINT.1
F2EM
MMMSK.1
F1EI
MMINT.0
F1EM
MMMSK.0
16.8 Registers
Table 78. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit
Number
Bit
Mnemonic Description
Data Receive Pointer Reset Bit
7
DRPTR
Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
97
4173E–USB–09/07
ATMEL [ ATMEL ]
