Bit
Bit
Number
Mnemonic Description
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
2
1
0
F1FM
F2EM
F1EM
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
Reset Value = 1111 1111b
Table 84. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit
Bit
Number
Mnemonic Description
MMC Command Receive Byte
Output (read) register of the response FIFO.
7 - 0
MC7:0
MMC Command Transmit Byte
Input (write) register of the command FIFO.
Reset Value = 1111 1111b
102
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
