Bit
Bit
Number
Mnemonic Description
Data Transmit Pointer Reset Bit
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
6
5
4
3
2
1
0
DTPTR
CRPTR
CTPTR
Command Receive Pointer Reset Bit
Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
MBLOCK Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
DFMT
RFMT
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
CRC7 Disable Bit
Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
CRCDIS
Reset Value = 0000 0000b
Table 79. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
7
6
5
4
3
2
1
0
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
Bit
Number
Bit
Mnemonic Description
Block Length Bits
7 - 4
BLEN3:0
DATDIR
Refer to Table 77 for Bits description. Do not program value > 1011b.
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
3
Data Transmission Enable Bit
2
DATEN
Set and clear to enable data transmission immediately or after response has
been received.
Response Enable Bit
1
0
RESPEN Set and clear to enable the reception of a response following a command
transmission.
Command Transmission Enable Bit
CMDEN
Set and clear to enable transmission of the command FIFO to the card.
Reset Value = 0000 0000b
Table 80. MMCON2 Register
98
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
