AT89C5132
the user may reset the data controller and its internal state machine by setting and clearing the
DCR bit in MMCON2 register.
This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of
frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4).
16.6.4.3
Data Reading
Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full
(F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.
Figure 16-18. Data Stream Reception Flows
Data Stream
Reception
Data Stream
Initialization
Data Stream
Reception ISR
Unmask FIFOs Full
F1FM = 0
F2FM = 0
FIFO Full?
F1FI or F2FI = 1?
FIFO Full?
F1FI or F2FI = 1?
FIFO Reading
read 8 data from MMDAT
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
No More Data
To Receive?
Mask FIFOs Full
F1FM = 1
F2FM = 1
Send
STOP Command
Send
a. Polling Mode
STOP Command
b. Interrupt Mode
95
4173E–USB–09/07
ATMEL [ ATMEL ]
