Figure 21-2. Timing Diagram
CLK
TADCLK
ADEN
TSETUP
ADSST
ADEOC
TCONV
21.1.1
Clock Generator
The ADC clock is generated by division of the peripheral clock (see details in Section “X2 Fea-
ture”, page 12). The division factor is then given by ADCP4:0 bits in ADCLK register. Figure 21-
3 shows the ADC clock generator and its calculation formula(1).
Figure 21-3. ADC Clock Generator and Symbol Caution:
ADCLK
PER
CLOCK
ADC
CLOCK
÷ 2
ADCD4:0
ADC Clock
ADC Clock Symbol
PERclk
ADCclk = -------------------------
2 ⋅ ADCD
Note:
1. In all cases, the ADC clock frequency may be higher than the maximum FADCLK parameter
reported in the Section “Analog to Digital Converter”, page 201.
2. The ADCD value of 0 is equivalent to an ADCD value of 32.
21.1.2
Channel Selection
The channel on which conversion is performed is selected by the ADCS bit in ADCON register
according to Table 30.
Table 30. ADC Channel Selection
ADCS
Channel
AIN1
0
1
AIN0
21.1.3
Conversion Precision
The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion
for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode(1),(2) is
enabled by setting the ADIDL bit in ADCON register(3). Thus, when conversion is launched (see
Section "Conversion Launching", page 149), the CPU core is stopped until the end of the con-
148
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
