AT89C5132
version (see Section "End Of Conversion", page 149). This bit is cleared by hardware at the end
of the conversion.
Notes: 1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle mode.
2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed,
according to their priority after the end of the conversion.
3. Concurrently with ADSST bit.
21.1.4
Configuration
The ADC configuration consists in programming the ADC clock as detailed in the Section "Clock
Generator", page 148. The ADC is enabled using the ADEN bit in ADCON register. As shown in
Figure 93, user must wait the setup time (TSETUP) before launching any conversion.
Figure 21-4. ADC Configuration Flow
ADC
Configuration
Program ADC Clock
ADCD4:0 = xxxxxb
Enable ADC
ADIDL = x
ADEN = 1
Wait Setup Time
21.1.5
Conversion Launching
The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set
during the conversion. As soon as the conversion is started, it takes 11 clock periods (TCONV
)
before the data is available in ADDH and ADDL registers.
Figure 21-5. ADC Conversion Launching Flow
ADC
Conversion Start
Select Channel
ADCS = 0-1
Start Conversion
ADSST = 1
21.1.6
End Of Conversion
The end of conversion is signalled by the ADEOC flag in ADCON register becoming set or by the
ADSST bit in ADCON register becoming cleared. ADEOC flag can generate an interrupt if
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4173E–USB–09/07
ATMEL [ ATMEL ]
