enabled by setting EADC bit in IEN1 register. This flag is set by hardware and must be reset by
software.
21.2 Registers
Table 31. ADCON Register
ADCON (S:F3h) – ADC Control Register
7
-
6
5
4
3
2
-
1
-
0
ADIDL
ADEN
ADEOC
ADSST
ADCS
Bit
Bit Number Mnemonic Description
Reserved
The value read from this bit is always 0. Do not set this bit.
7
6
-
ADC Pseudo-Idle Mode
Set to suspend the CPU core activity (pseudo-idle mode) during conversion.
Clear by hardware at the end of conversion.
ADIDL
ADC Enable Bit
Set to enable the A to D converter.
Clear to disable the A to D converter and put it in low power stand by mode.
5
4
ADEN
End Of Conversion Flag
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
ADEOC
Start and Status Bit
3
2 - 1
0
ADSST
-
Set to start an A to D conversion on the selected channel.
Cleared by hardware at the end of conversion.
Reserved
The value read from these bits is always 0. Do not set these bits.
Channel Selection Bit
ADCS
Set to select channel 0 for conversion.
Clear to select channel 1 for conversion.
Reset Value = 0000 0000b
Table 32. ADCLK Register
ADCLK (S:F2h) – ADC Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
ADCD4
ADCD3
ADCD2
ADCD1
ADCD0
Bit
Bit Number Mnemonic Description
Reserved
The value read from these bits is always 0. Do not set these bits.
7 - 5
4 - 0
-
ADC Clock Divider
ADCD4:0
5-bit divider for ADC clock generation.
Reset Value = 0000 0000b
150
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
