AT85C51SND3Bx
Bit
Bit
Number
Mnemonic Description
Cycle Type Selection
Set to select non normalized access cycles (6800 or 8080 interface).
Clear to select normalized access cycles (6800 or 8080 interface).
3
2
1
LCYCT
LCEN
LCRD
LCD Interface Enable
Set to enable the LCD Interface.
Clear to disable the LCD Interface.
LCD Read Command
Set to initiate a read data or status register from LCD controller.
Cleared by hardware at the end of read.
LCD Register Select
Set to output high level on LA0/LRS pin during next read or write access.
Clear to output low level on LA0/LRS pin during next read or write access.
This value depends on the LCD controller.
0
LCRS
Reset Value= 0000 0000b
Table 257. LCDSTA Register
LCDSTA (1.8Fh) – LCD Status Register
7
6
5
4
3
-
2
-
1
-
0
-
-
-
-
LCBUSY
Bit
Bit
Number
Mnemonic Description
Reserved
7:1
0
-
The value read from these bits is always 0. Do not set these bits.
Busy Flag
LCBUSY
Set by hardware during any access to the LCD controller and while LCD
controller is busy if busy check process is enabled.
Reset Value= 0000 0000b
Table 258. LCDBUM Register
LCDBUM (1.8Dh) – LCD Busy Mask Register
7
6
5
4
3
2
1
0
BUM7
BUM6
BUM5
BUM4
BUM3
BUM2
BUM1
BUM0
Bit
Bit
Number
Mnemonic Description
Busy Mask
Set bits to be checked during the busy check process and thus enable the busy
check process.
7:0
BUM7:0
Clear all bits to disable the busy check process.
Reset Value= 0000 0000b
237
7632A–MP3–03/06
ATMEL [ ATMEL ]
