Registers
Table 260. KBCON Register
KBCON (0.A3h) – Keyboard Control Register
7
6
5
4
3
2
1
0
KINL3
KINL2
KINL1
KINL0
KINM3
KINM2
KINM1
KINM0
Bit
Bit
Number
Mnemonic Description
Keyboard Input Level Bit
7-4
3-0
KINL3:0
KINM3:0
Set to enable a high level detection on the respective KIN3:0 input.
Clear to enable a low level detection on the respective KIN3:0 input.
Keyboard Input Mask Bit
Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.
Reset Value = 0000 1111b
Table 261. KBSTA Register
KBSTA (0.A4h) – Keyboard Control and Status Register
7
6
5
4
-
3
2
1
0
KPDE
KDCPE
KDCPL
KINF3
KINF2
KINF1
KINF0
Bit
Bit
Number
Mnemonic Description
Keyboard Power Down Enable Bit
7
6
KPDE
Set to enable exit of power down mode by the keyboard interrupt.
Clear to disable exit of power down mode by the keyboard interrupt.
Keyboard DCPWR Pin Enable
KDCPE
Set to connect DCPWR pin on KIN0 input.
Clear to isolate DCPWR pin from KIN0 input.
Keyboard DCPWR Pin Line
5
4
KDCPL
-
Set by hardware and represent the level on DCPWR input.
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Input Interrupt Flag
3-0
KINF3:0
Set by hardware when the respective KIN3:0 input detects a programmed level.
Cleared when reading KBSTA.
Reset Value = 0010 0000b
240
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
