AT85C51SND3Bx
Bit
Bit
Number
Mnemonic Description
Transmission Interrupt Flag
Set by hardware when the Tx FIFO is not full: a character can be loaded through
SBUF.
Cleared by hardware when the Tx FIFO becomes full: no more character can be
loaded.
1
0
TI
Reception Interrupt Flag
Set by hardware when the Rx FIFO is not empty: character ready to be read
through SBUF.
RI
Cleared by hardware when the Rx FIFO becomes empty: no more character to
be read.
Reset Value = 0X10 0010b
Table 245. SIEN Register
SIEN (1.A9h) – SIO Interrupt Enable Register
7
6
5
4
3
2
1
0
-
-
EOTIE
OEIE
PEIE
FEIE
TIE
RIE
Bit
Bit
Number
Mnemonic Description
Reserved
7-6
5
-
The value read from these bits is always 0. Do not set these bits.
End Of Transmission Interrupt Enable Bit
EOTIE
OEIE
PEIE
FEIE
TIE
Set to enable end of transmission interrupt generation.
Clear to disable end of transmission interrupt generation.
Overrun Error Interrupt Enable Bit
4
3
2
1
0
Set to enable overrun error interrupt generation.
Clear to disable overrun error interrupt generation.
Parity Error Interrupt Enable Bit
Set to enable parity error interrupt generation.
Clear to disable parity error interrupt generation.
Framing Error Interrupt Enable Bit
Set to enable framing error interrupt generation.
Clear to disable framing error interrupt generation.
Transmission Interrupt Enable Bit
Set to enable transmission interrupt generation.
Clear to disable transmission interrupt generation.
Reception Interrupt Enable Bit
RIE
Set to enable reception interrupt generation.
Clear to disable reception interrupt generation.
Reset Value = 0000 0000b
221
7632A–MP3–03/06
ATMEL [ ATMEL ]
