Table 243. SFCON Register
SFCON (0.95h) – SIO Flow Control Register
7
6
5
4
3
2
1
0
OVRSF3
OVRSF2
OVRSF1
OVRSF0
CTSEN
RTSEN
RTSTH1
RTSTH0
Bit
Bit
Number
Mnemonic Description
Over Sampling Factor Bits
7-4
3
OVRSF3:0
CTSEN
Number of time a data bit is sampled for level determination.
Oversampling factor = OVRSF3:0 + 1.
Clear To send Enable Bit
Set to enable transmission hardware flow control using CTS signal.
Clear to disable transmission hardware flow control.
Request To send Enable Bit
2
RTSEN
Set to enable reception hardware flow control using RTS signal.
Clear to disable reception hardware flow control.
Request To send Assertion Threshold
1-0
RTSTH1:0
Refer to Table 241 for information on threshold values.
Reset Value = 0000 0000b
Table 244. SINT Register
SINT (1.A8h) – SIO Interrupt Source Register
7
6
5
4
3
2
1
0
-
-
EOTI
OEI
PEI
FEI
TI
RI
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is always 0. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
End Of Transmission Interrupt Flag
Set by hardware when both Tx FIFO and Tx shift register are empty: actual end
of transmission.
Cleared by hardware when the Tx FIFO or Tx shift register are not empty.
5
4
EOTI
Overrun Reception Error Interrupt Flag
Set by hardware when a character is received while the Rx shift register is full
(Rx FIFO full).
OEI
Clear by software to acknowledge interrupt.
Parity Reception Error Interrupt Flag
3
2
PEI
FEI
Set by hardware when a parity error occurs in a received character.
Clear by software to acknowledge interrupt.
Framing Reception Error Interrupt Flag
Set by hardware when a framing error occurs in a received character.
Clear by software to acknowledge interrupt.
220
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
