AT8xC51SND2C
Synchronous
Peripheral Interface
The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and
slave modes capability.
Figure 102 shows an SPI bus configuration using the AT8xC51SND2C as master con-
nected to slave peripherals while Figure 103 shows an SPI bus configuration using the
AT8xC51SND2C as slave of an other master.
The bus is made of three wires connecting all the devices together:
•
•
•
Master Output Slave Input (MOSI): it is used to transfer data in series from the
master to a slave.
It is driven by the master.
Master Input Slave Output (MISO): it is used to transfer data in series from a slave
to the master.
It is driven by the selected slave.
Serial Clock (SCK): it is used to synchronize the data transmission both in and out
the devices through their MOSI and MISO lines. It is driven by the master for eight
clock cycles which allows to exchange one Byte on the serial lines.
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one
slave, it may be continuously selected with SS tied to a low level. Otherwise, the
AT8xC51SND2C may select each device by software through port pins (Pn.x). Special
care should be taken not to select 2 slaves at the same time to avoid bus conflicts.
Figure 102. Typical Master SPI Bus Configuration
Pn.z
Pn.y
LCD
Controller
Pn.x
SS
SS
SS
DataFlash 1
DataFlash 2
SO
SI
SCK
SO
SI
SCK
SO
SI
SCK
AT8xC51SND2C
MISO
P4.0
P4.1
P4.2
MOSI
SCK
Figure 103. Typical Slave SPI Bus Configuration
SSn
SS1
SS
AT8xC51SND2C
Slave n
SS0
SS
SS
Slave 1
Slave 2
SO
SI
SCK
SO
SI
SCK
MISO MOSI SCK
MASTER
MISO
MOSI
SCK
157
4341D–MP3–04/05
ATMEL [ ATMEL ]
