AT8xC51SND2C
Table 148. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
7
-
6
-
5
4
3
2
1
0
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The value read from these bits is always 0. Do not set these bits.
Card Busy Flag
CBUSY Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
CRC16 Status Bit
Transmission mode
Set by hardware when the token response reports a good CRC.
CRC16S Cleared by hardware when the token response reports a bad CRC.
Reception mode
4
3
Set by hardware when the CRC16 received in the data block is correct.
Cleared by hardware when the CRC16 received in the data block is not correct.
Data Format Status Bit
Transmission mode
Set by hardware when the format of the token response is correct.
DATFS
CRC7S
Cleared by hardware when the format of the token response is not correct.
Reception mode
Set by hardware when the format of the frame is correct.
Cleared by hardware when the format of the frame is not correct.
CRC7 Status Bit
Set by hardware when the CRC7 computed in the response is correct.
Cleared by hardware when the CRC7 computed in the response is not correct.
2
1
This bit is not relevant when CRCDIS is set.
Response Format Status Bit
RESPFS Set by hardware when the format of a response is correct.
Cleared by hardware when the format of a response is not correct.
Command FIFO Lock Bit
Set by hardware to signal user not to write in the transmit command FIFO: busy
0
CFLCK
state.
Cleared by hardware to signal user the transmit command FIFO is available: idle
state.
Reset Value = 0000 0000b
153
4341D–MP3–04/05
ATMEL [ ATMEL ]
