AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.13.2 UART Register Descriptions
All registers are 8 bits wide. Registers are selected based on the address and the value of Divisor Latch Select (DLS) bit in the line control register
(UART_LNCTR_REG).
Table 76 UART registers
Register Name
UART_DATA_REG
Base Address
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
AS3525_UART_BASE
Offset
0x00
0x00
0x04
0x04
0x08
0x0C
0x10
0x14
DLS
Note
Data register (Rx / Tx)
Clock divider lower byte register
Clock divider higher byte register
Interrupt enable register
Interrupt status register
FIFO control register
0
1
1
0
UART_DLO_REG
UART_DHI_REG
UART_INTEN_REG
UART_INTSTATUS_REG
UART_FCTL_REG
UART_LNCTL_REG
UART_LNSTATUS_REG
Line control register
Line status register
Table 77 UART Data Register
Name
Base
AS3525_UART_BASE
Data register
Default
UART_DATA_REG
0xC8110000
Holds the data byte received or the data byte to be transmitted respectively.
RX:
This register holds the received data byte.
In FIFO mode, this byte will be the top byte of the 16-byte FIFO.
If FIFO mode is disabled, it will be the content of the receive shift register after a byte has been
shifted in.
A read to the address value 3b000 with Divisor Latch Select (DLS) bit 1’b0 will give the content of
this register.
If a character less than 8 bits is received, extra zero bits will be padded to this register.
Offset: 0x00
DLS bit set to 0
TX:
This register contains the data to be transmitted. This register will be written by the processor.
In FIFO mode, a write to this address will write data into the FIFO.
In FIFO mode, top byte of txFIFO is passed on to transmitter shift register.
If FIFO is disabled, a write to the address 3’b000 with DLS bit 1’b0 will write into this register.
If FIFO is disabled, this register will be overwritten with new data.
If FIFO is disabled, data in this register will be passed on to transmitter shift register.
Bit
Bit Name
Default
Access
Bit Description
7:0
UART_DATA_REG
00000000 RW
Holds the data byte received or the data byte to be transmitted
respectively.
Table 78 UART Clock divider lower byte register
Name
Base
Default
UART_DLO_REG
AS3525_UART_BASE
0xC8110000
Clock divider lower byte register
This register holds the clock divider value (decimal) which is used to derive the baud
clock. To achieve a desired baud rate, the baud clock should be 16-times higher then
the baud rate. To derive this clock the ratio of the system clock and the required baud
clock should be calculated and the value should be programmed into the clock divider
lower byte and higher byte registers (UART_DLO_REG and UART_DHI_REG).
Clock divider value = (input frequency) / (baud rate x 16)
Offset: 0x00
DLS set to 1
Bit
Bit Name
Default
Access
Bit Description
7:0
UART_DLO_REG
00000000
W
This register holds the lower byte of the decimal divisor value
to calculate baud clock.
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