AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.13.1 UART Baud Generator and Clock Divider Settings
The internal baud generator module generates the required baud clock using the divisor register value. To achieve correct synchronizationincoming
bits are over sampled by a factor of 16x. Software should program the divisor value by which the system clock has to be divided to achieve the
required baud clock frequency.
The equation to calculate baud divisor is
Baud Divisor = (input frequency) ÷ (baud rate x 16)
Important: the internal clock divider must be set to a value of 2 or higher. Setting the value to 1 (no division) is not allowed!
For example, for 16 MHz PCLK clock following table gives the list of settings for different BAUD rates.
Baud Rate
Required Baud
clock frequency
800
Decimal
divisor value
20000
50
75
1200
13333
9091
7435
6667
3333
1667
833
556
500
208
139
104
52
110
1760
134.5
150
2152
2400
300
4800
600
9600
1200
1800
2000
4800
7200
9600
19200
38400
56000
128000
250000
300000
500000
19200
28800
32000
76800
115200
153600
307200
614400
896000
204800
4000000
4800000
8000000
26
18
8
4
3
2
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