AS3525-A/-B C22O22
Data Sheet, Confidential
Name
Base
Default
UART_INTSTATUS_REG
AS3525_UART_BASE
0xC8110000
Interrupt status register
This register will give the status of the interrupt. Depending on the enabled interrupt
bits in the interrupt enable register (UART_INTEN_REG) different interrupts will be
generated and the status will be updated in this register. On sensing an interrupt the
software should read this register to get the status of the interrupt.
Offset: 0x08
Bit
Bit Name
rxDataRdy
Default
Access
Bit Description
This is the data ready interrupt.
0
0
RU
In FIFO mode this bit is set when the number of bytes in the
FIFO reaches the trigger level. This bit is also set in FIFO
mode when a timeout occurs in the reception, i.e. Rx line idle
for more than 4 char times and there is data in the FIFO.
If FIFO mode is disabled this bit is set when one full byte is
received.
This bit is cleared when the FIFO is empty or the data register
(UART_DATA_REG (Rx)) is read.
Table 82 UART FIFO control register
Name
Base
AS3525_UART_BASE
FIFO control register
Default
UART_FCTL_REG
0xC8110000
Offset: 0x0C
This register holds the control parameters to control receive (rx) and transmit (tx) FIFO.
The parameters will enable the FIFOs, set the receiver trigger level, etc.
Bit
Bit Name
Default
000
00
Access
Bit Description
7:5
4:3
Reserved
trigLevel
These bits are reserved for future use.
These two bits will select the trigger level for the rxFIFO. Once
W
the FIFO pointer reaches this level rxDataRdy interrupt is
asserted.
00: 01 byte
01: 04 bytes
10: 08 bytes
11: 14 bytes
2
1
0
rxFIFORst
txFIFORst
0
0
0
W
W
W
This bit will reset rxFIFO pointers and clear all the bytes in the
rxFIFO.
This bit is self clearing, i.e. after resetting FIFO this bit will
become zero.
This bit will reset txFIFO pointers and clear all the bytes in the
txFIFO.
This bit is self clearing, i.e. after resetting FIFO this bit will
become zero.
FIFOModeEn
This bit will enable the FIFO mode. By default this will be
reset.
Table 83 UART Line control register
Name
Base
AS3525_UART_BASE
Line control register
Default
UART_LNCTL_REG
0xC8110000
Offset: 0x10
Bit Name
This register controls the asynchronous data. Parameters in this register set the
transmit and receive character format, the data length, parity bit, stop bit length, etc.
Bit
Default
Access
Bit Description
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