AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.12.7 Clock frequencies
The input clock is directly taken from the PCLK clock. A programmable prescaler is implemented within the CGU. Input clock for the prescaler is in
the range of 20 - 60 MHz.
Programmable division factors for the prescaler in the range of 1 to 8. Input clock to the module is in the range of 2.5 to 60 MHz.
Within the module the control signal generator is doing a division by 16 or 32 (selectable). So the effective output data rates are in the range of 1.25
to 4 MHz for maximum performance and can be scaled down in the range of 0.07 to 0.25 MHz.
Figure 38 DBOP data rate
C0
Clock
PCLK
(APB clock)
c1
c2
Control
signal
generator
clk_dbop
prescaler
(inside
CGU)
c3
predivider 1 to 8
Divider /16 or /32
Output data rate
4.06 MHz
65 MHz
8.125 MHz
65 MHz
...
0.25 MHz
20 MHz
20 MHz
2.5 MHz
1.25 MHz
0.07 MHz
Time constraining for the module should be done with 65 MHz, if there is a demand the time constraints for the output pads can be reduced.
7.3.12.8
Interface with GPIO PINs / additional PINs
For the SW, the usage of either ARM primecell GPIO ports or DBOP port can be configured with the GPIOAFSEL registers.
Following IO ports are used for the basic 8 bit interface
xpc[7:0]
xpb[3:0]
for dout[7:0] and din[7:0]
for {C3, C2, C1, C0}
Following IO ports are used for the optional 16 bit interface
xpb[7:4]
for dout[11:8] and din[11:8]
dbop_d[15:12] for dout[15:12] and din[15:12]
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