AS3525-A/-B C22O22
Data Sheet, Confidential
Table 79 UART Clock divider higher byte register
Name
UART_DHI_REG
Offset: 0x04
Base
Default
AS3525_UART_BASE
0xC8110000
Clock divider higher byte register
DLS set to 1
This register holds the higher byte of the decimal divisor value to calculate baud clock.
Bit
Bit Name
Default
Access
Bit Description
7:0
UART_DHI_REG
00000000
W
This register holds the higher byte of the decimal divisor value
to calculate baud clock.
Table 80 UART Interrupt enable register
Name
Base
AS3525_UART_BASE
Interrupt enable register
Default
UART_INTEN_REG
0xC8110000
Offset: 0x04
This register will enable the three types of interrupts. Setting the bits of this register to
logic 1 enables the selected interrupt.
DLS set to 0
Bit
Bit Name
Default
Access
Bit Description
7:3
2
1
Reserved
lnStatusEn
txDataEmptyEn
rxDataRdyEn
00000
These bits are reserved for future use.
This bit enables the “rxLineStatus” interrupt.
This bit enables the “txDataEmpty” interrupt.
This bit enables the “rxDataRdy” interrupt.
0
0
0
W
W
W
0
Table 81 UART Interrupt status register
Name
Base
AS3525_UART_BASE
Interrupt status register
Default
0xC8110000
UART_INTSTATUS_REG
This register will give the status of the interrupt. Depending on the enabled interrupt
bits in the interrupt enable register (UART_INTEN_REG) different interrupts will be
generated and the status will be updated in this register. On sensing an interrupt the
software should read this register to get the status of the interrupt.
Offset: 0x08
Bit
Bit Name
Default
Access
Bit Description
7:3
2
Reserved
rxLineStatus
00000
0
These bits are reserved for future use.
RU
This interrupt is set on any error condition on the receive line.
There are four types of error possibilities. These error
conditions are set in bits 4:1 of the line status register
(UART_LNSTATUS_REG).
This bit is reset on a read of the line status register
(UART_LNSTATUS_REG).
1
txDataEmpty
0
RU
In FIFO mode this bit is set when txFIFO is empty.
If FIFO mode is disabled this interrupt is set if the data register
(UART_DATA_REG (Tx)) is empty.
This bit will be reset on write to the data register
(UART_DATA_REG (Tx)).
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