欢迎访问ic37.com |
会员登录 免费注册
发布采购

A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号A3525BC21O22TRA的Datasheet PDF文件第87页浏览型号A3525BC21O22TRA的Datasheet PDF文件第88页浏览型号A3525BC21O22TRA的Datasheet PDF文件第89页浏览型号A3525BC21O22TRA的Datasheet PDF文件第90页浏览型号A3525BC21O22TRA的Datasheet PDF文件第92页浏览型号A3525BC21O22TRA的Datasheet PDF文件第93页浏览型号A3525BC21O22TRA的Datasheet PDF文件第94页浏览型号A3525BC21O22TRA的Datasheet PDF文件第95页  
AS3525-A/-B C22O22  
Data Sheet, Confidential  
7.3.12.5 DIN register  
With the dinStrobe, data are written to the DIN register. This gives a simple mechanism, in which for example the status data can be read from a  
LCD display interface.  
To do a data read, first the START READ (strd) bit is programmed into the control register. With START READ, the control signal generator starts  
to generate one cycle with the according control signals. Data are strobed by the programmed strobe time into the din register. After the cycle is  
completed the HW resets the strd bit to 0. With set of the strd bit, the rd_data_valid bit is also reseted.  
The SW just has to poll the rd_data_valid bit, when the bit gets set the input data can be read from the din register. After read cycle, the control  
signal generator returns to the quiescent state.  
Following timing diagram shows an example of three read cycles.  
Figure 37 DBOP read cycle example  
Read cycle 0  
Read cycle 1  
Read cycle 2  
C0 (= read_n)  
Data input  
xx  
D0  
D1  
D2  
Read strobe  
DIN register  
strd  
D0  
D1  
D2  
rd_data_valid  
Note: Be aware that the read cycle should only be activated when there is no active write cycle (FiFo is empty). Otherwise the results of such action  
get unpredictable.  
For any read cycle, the write enable bit must be set to 0 (write disabled).  
start read  
(strd)  
write enable  
(wen)  
FiFo empty  
Status  
DBOP function  
quiescent  
quiescent  
valid write  
quiescent  
valid read  
valid read  
valid write  
quiescent  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.3.12.6 Interrupt Generator  
Depending on the FiFo Status, an interrupt request can be generated. The conditions that cause an interrupt are set within the control register.  
The interrupt output DBOPIRQ is active high.  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com  
Revision 1.13  
91 - 194  
 复制成功!