AS3525-A/-B C22O22
Data Sheet, Confidential
Name
Base
Default
UART_LNCTL_REG
AS3525_UART_BASE
0xC8110000
Line control register
Offset: 0x10
This register controls the asynchronous data. Parameters in this register set the
transmit and receive character format, the data length, parity bit, stop bit length, etc.
Bit
Bit Name
Default
Access
Bit Description
7
DLS
0
RW
Divisor Latch Select Bit. This bit is used to select Divisor Latch
registers.
1: Divisor Latch registers can be accessed. To access other
registers this bit should be zero.
6
5
4
3
2
breakCntl
stickParity
evenParity
parityEn
0
0
0
0
0
RW
RW
RW
RW
RW
1: Will cause a break condition to be transmitted, i.e. TX line is
pulled low. Normal transmission can be recovered once this bit
is cleared. Transmitter logic can be used as break timer.
1: If this bit is set, along with parityEn a fixed parity bit will be
transmitted and expected. This fixed parity bit will be the
complement of the bit 4.
0: Data byte along with parity bit will be sent and expected to
be odd parity.
1: Data byte along with the parity bit will be even parity.
Enable parity bit.
0: Data byte will be transmitted and received without parity bit.
1: Will enable the parity bit at the end of the data byte.
This bit decides how many stop bits should be sent along with
a data byte.
stopBits
0: 1 stop bit transmitted
1: 2 stop bits transmitted if 6, 7 or 8 bit wordLenSel
1: 1.5 stop bits transmitted if 5 bit wordLenSel
Receiver will always check for one stop bit.
These bits will select the number of data bits to be transmitted
and received.
1:0
wordLenSel
00
RW
00: 5 bits
01: 6 bits
10: 7 bits
11: 8 bits
Table 84 UART Line status register
Name
Base
AS3525_UART_BASE
Line status register
Default
UART_LNSTATUS_REG
0xC8110000
Offset: 0x14
This register holds the status information of the data transfer. It gives information about
the received data.
Bit
Bit Name
Default
Access
Bit Description
7
FIFODataError
0
RU
1: This bit is set when any data character in the FIFO has
parity or framing error or break condition.
0: This bit is reset once the line status register
(LINE_STATUS_REG) is read.
6
5
Reserved
txHoldRegEmpty
0
0
This bit is reserved for future use.
RU
This bit is associated with the txDataEmpty interrupt.
1: Indicates that there is no data in txFIFO or the data register
(UART_DATA_REG (Tx)). This bit is set once the data is
shifted out.
0: This bit is reset once data is written into the data register
(UART_DATA_REG (Tx)).
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