AS3525-A/-B C22O22
Data Sheet, Confidential
Name
Base
Default
-
NAFStatus
AS3525_NAND_FLASH_BASE
Status Register
Offset 0x0014
The NAFStatus register contains information on the internal status.
Bit
Bit Name
Defau Access
lt
Bit Description
NAFWords empty and Controller ready indication (edge
triggered)
0: when bit 2 of NAFClear register is set to ‘1’
1: when read/write strobe changes from ‘0’ to ‘1’ (end of
strobe) and NAFWords register has become empty.
Note: This bit is used to detect the end of a multiple read/write
burst transaction
Read/write strobe ready indication (edge triggered)
0: when bit 1 of NAFClear register is set to ‘1’
1: when read/write strobe changes from ‘0’ to ‘1’ (end of
strobe)
Note: read/write strobes can last from 3 to 33 PCLK cycles
depending on NAFConfig settings.
NAFWords empty and Controller ready indication (edge
triggered)
2
1
0
got_empty_and_rdy
0x0
0x0
0x0
R
R
R
got_strobe_ready
got_flash_ready
0: when bit 2 of NAFClear register is set to ‘1’
1: when read/write strobe changes from ‘0’ to ‘1’ (end of
strobe) and NAFWords register has become empty.
Note: This bit is used to detect the end of a multiple read/write
burst transaction
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com Revision 1.13
79 - 194
AMSCO [ AMS(艾迈斯) ]
