AS3525-A/-B C22O22
Data Sheet, Confidential
Table 61 NAF status register
Name
Base
Default
-
NAFStatus
AS3525_NAND_FLASH_BASE
Status Register
Offset 0x0014
The NAFStatus register contains information on the internal status.
Bit
Bit Name
Defau Access
lt
Bit Description
FIFO error signal
0: if FIFO is reset
1: if FIFO contains 36 words and FIFO push(write) has
occurred or when FIFO contains 0 words and a FIFO pop(read)
has occurred. The FIFO error will lock the FIFO and has to be
reset by a reset of the FIFO (by setting NAFControl register bit
1 to ‘1’)
13
fifo_error
0x0
R
FIFO full signal
12
11
10
9
fifo_full
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
0: if FIFO contains less than 36 words
1: if FIFO contains 36 words
FIFO almost_full signal
0: if FIFO contains less than 32 words
1: if FIFO contains more than or equal 32 words
fifo_almost_full
fifo_almost_empty
fifo_empty
FIFO almost_empty signal
0: if FIFO contains more than 4 words
1: if FIFO contains less than or equal 4 words
FIFO empty signal
0: if FIFO contains more than 0 words
1: = when FIFO contains 0 words
read/write strobe ready signal
0: if read/write strobe ‘0’ (strobe active)
1: if read/write strobe ‘1’ (strobe inactive)
8
strobe_ready
flash_ready
synchronised NAND flash ready signal
0: if synchronised input ‘naf_busy_in_n’ is ‘0’ (busy)
1: if synchronised input ‘naf_busy_in_n’ is ‘1’ (ready)
7
FIFO error indication (edge triggered)
0: if bit 6 of NAFClear register is set to ‘1’
1: if FIFO contains 36 words and FIFO push(write) occurs or
when FIFO contains 0 words and a FIFO pop(read) occurs.
6
5
got_fifo_error
got_fifo_full
0x0
0x0
R
R
FIFO full indication (edge triggered)
0: if bit 5 of NAFClear register is set to ‘1’
1: if FIFO contains 36.
FIFO high indication (edge triggered)
0: if bit 4 of NAFClear register is set to ‘1’
1: if FIFO gets full (36 words) or changes from 31 to 32 words
(and when the NAFWords register is greater than 32).
Note: When this bit gets ‘1’ during ‘Page Read’ mode, a new
FIFO burst read of up to 32 words is possible.
FIFO low indication (edge triggered)
0: if bit 3 of NAFClear register is set to ‘1’
1: if FIFO gets empty or changes from 5 to 4 words (and when
the NAND Flash requires more than 32 bytes/halfwords).
Note: When this bit gets ‘1’ during ‘Page Programming’ mode,
a new FIFO burst write of up to 32 words is possible
4
3
got_fifo_high
got_fifo_low
0x0
0x0
R
R
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