AS3525-A/-B C22O22
Data Sheet, Confidential
Table 59 NAF data register
Name
Base
Default
0x0000
NAFData
AS3525_NAND_FLASH_BASE
Data Register
Offset 0x000C
The NAFData register offers unbuffered access to the data bus of the NAND flash
device.
Bit
15:0
Bit Name
NAFData
Default Access
Bit Description
For X8 devices (8-bit data bus) only bits 7:0 are relevant, other
bits are ignored
0x01 R/W
For X16 devices (16-bit data bus) all are relevant
Table 60 NAF mode register
Name
Base
Default
0x00
NAFMode
AS3525_NAND_FLASH_BASE
Mode register
Offset 0x0010
The NAFMode register controls NAND flash read/write/erase procedures.
Default Access Bit Description
Bit
Bit Name
0: write protection is on
1: write protection is off (when ‘power_on’ is 1)
7
write protection
0x0
R/W
0: error code correction disabled
1: error code correction enabled (when ‘ce’ is 1)
2: stop error code correction, disable read/write strobes and
disable ‘naf_do’ (when ‘ce’ is 1). Use this mode when reading
the NAFEcc register
6:5
ecc [1:0]
0x0
R/W
3: Reset NAFEcc register contents, ‘ecc’ changes to value 1
(enable mode) automatically after the next PCLK cycle
controls ‘chip enable’
4
3
2
1
0
ce
0x0
0x0
0x0
0x0
0x0
R/W
R
0: output ‘naf_ce_n’ is set to ‘1’ (device is disabled)
1: output ‘naf_ce_n’ is set to ‘0’ (device is enabled)
-
always ‘0’
0: power off (all output enable signals are turned off)
1: power on
power_on
ale
R/W
R/W
R/W
controls ‘address latch enable’
0: output ‘naf_ale’ is set to ‘0’
1: output ‘naf_ale’ is set to ‘1’ (Address Latch Cycle)
controls ‘command latch enable’
0: output ‘naf_cle’ is set to ‘0’
cle
1: output ‘naf_cle’ is set to ‘1’ (Command Latch Cycle)
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