AS3525-A/-B C22O22
Data Sheet, Confidential
Table 57 NAF control register
Name
Base
Default
0x2
NAFControl
AS3525_NAND_FLASH_BASE
NAFControl Register
The NAFControl register controls read access and FIFO dynamic reset.
Offset 0x0004
Bit
Bit Name
Default Access
Bit Description
1: triggers a FIFO reset pulse (when NAFConfig bit
‘fifo_staticreset_n’ is 1) The bit is cleared automatically in the
next PCLK cycle.
1
0
read_strobe
0x1
0x1
W
W
1: triggers one single read cycle on output ‘naf_re_n’. The bit
is cleared automatically in the next PCLK cycle.
fifo_reset_strobe
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