AS3525-A/-B C22O22
Data Sheet, Confidential
Table 58 NAF error correction register
Name
Base
Default
0x2
NAFEcc
AS3525_NAND_FLASH_BASE
NAF Error correction code register
The NAFEcc register offers access to the error correction code registers.
Offset 0x0008
Bit
Bit Name
Default Access
Bit Description
This register can be accessed up to 8 times and contains the
following data:
1.access => Line Parity Block1
2.access => Column Parity Block1**
3.access => Line Parity Block2
32:0
Nafecc [32:0]
0x0001
R
4.access => Column Parity Block2**
5.access => Line Parity Block3
6.access => Column Parity Block3**
7.access => Line Parity Block4
8.access => Column Parity Block4**
(9.access => same as 1.access)
Note: * Before access to NAFEcc registers is possible, NAFMode register has to be set to 0xd4 (after page write operation) or
to 0x54 (after page read operation). NAFEcc register contents will be cleared if NAFMode register bits 6 and 5 are both ‘1’.
** Only bits 11 to 0 are relevant for column parity, other bits are ‘0’;
The content of NAFEcc depends on the device type.
X8 (8-bit data bus) devices:
Line Parity Block1 : will contain the line
Column Parity Block1 : will contain the column
Line Parity Block2 : will contain the line
Column Parity Block2 : will contain the column
Line Parity Block3 : will contain the line
Column Parity Block3 : will contain the column
Line Parity Block4 : will contain the line
Column Parity Block4 : will contain the column
parity of byte 1 to 512 (after 512 r/w cycles)
parity of byte 1 to 512 (after 512 r/w cycles)
parity of byte 513 to 1024 (after 1024 r/w cycles)
parity of byte 513 to 1024 (after 1024 r/w cycles)
parity of byte 1025 to 1536 (after 1536 r/w cycles)
parity of byte 1025 to 1536 (after 1536 r/w cycles)
parity of byte 1537 to 2048 (after 2048 r/w cycles)
parity of byte 1537 to 2048 (after 2048 r/w cycles)
X16 (16-bit data bus) devices:
Line Parity Block1 : will contain the line
Column Parity Block1 : will contain the column
Line Parity Block2 : will contain the line
Column Parity Block2 : will contain the column
Line Parity Block3 : will contain the line
Column Parity Block3 : will contain the column
Line Parity Block4 : will contain the line
Column Parity Block4 : will contain the column
parity of halfword(7:0) 1 to 512 (after 512 r/w cycles)
parity of halfword(7:0) 1 to 512 (after 512 r/w cycles)
parity of halfword(15:8) 1 to 512 (after 512 r/w cycles)
parity of halfword(15:8) 1 to 512 (after 512 r/w cycles)
parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles)
parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles)
parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles)
parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles)
Note: Read ECC is not performed in unbuffered READ mode (this means when CPU accesses the Nand Flash through the
NAF_DATA registers)
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