AS3525-A/-B C22O22
Data Sheet, Confidential
Table 46 I2S input status register
Name
Base
Default
0x00
I2SIN_STATUS
AS3525_I2SIN_BASE
Status register
The status register is a read-only register. A read to this register returns the value
of the raw status bits AND’ed with the corresponding mask of enable bits set in the
mask register.
Offset: 0x000C
Bit
Bit Name
Default
Access
Bit Description
7
stereo24_status
0
R
Status of write interface for 24 bit stereo mode
0: left audio sample will be transferred next
1: right audio sample will be transferred next
1 if FIFO PUSH error
1 if FIFO POP is empty
1 if FIFO POP is almost empty
1 if FIFO POP is half full
1 if FIFO POP is almost full
1 if FIFO POP is full
1 if FIFO POP error
6
5
4
3
2
1
0
I2SIN_PUER
I2SIN_POE
I2SIN_POAE
I2SIN_POHF
I2SIN_POAF
I2SIN_POF
0
0
0
0
0
0
0
R
R
R
R
R
R
R
I2SIN_POER
Table 47 I2S Input interrupt clear register
Name
Base
Default
0x00
I2SIN_CLEAR
AS3525_I2SIN_BASE
Interrupt clear register
The interrupt clear register is a write-only register. The corresponding static status
bit can be cleared by writing a 1 to the corresponding bit in the clear register. All
other interrupt flags are level interrupts depending on the status of the FIFO. The
bits are de-asserted depending on the FIFO controller.
Offset: 0x0010
Bit
Bit Name
reserved
I2SIN_clear_puer
reserved
Default
Access
Bit Description
Clear PUSH error interrupt flag
Clear POP error interrupt flag
7
6
5:1
0
W
W
W
W
I2SIN_clear_poer
I2SIN_DATA
The I2SINIF provides a single 32 bit wide data register. The register is used to read the audio samples from FIFO. If 14 bit mode is selected, both
the left and right data are made available in the same register. Otherwise in the 24 bit mode the left and right data are provided through the same
register alternatively. The stereo24_status bit in the I2SIN_STATUS register provides information which channel’s data will be provided next. The
14bit_mode bit in the I2SIN_CONTROL register defines how the values are read from the FIFO.
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