AS3525-A/-B C22O22
Data Sheet, Confidential
The following table shows the valid combinations for sdata_source (bit 7 and 6) and i2s_clk_source (bit 9 and 8) of the I2SIN_CONTROL register.
sdata_source
i2s_clk_source
Description
default mode (AFE with AS3525)
00
01
01
10
11
00
00
11
10
00
external data, external clock
external data, internal clock
data and clock from SPDIF converter
loopback, internal data and clock
Table 44 I2S Input mask register
Name
Base
Default
0x00
I2SIN_MASK
AS3525_I2SIN_BASE
Interrupt mask register
Offset: 0x0004
The interrupt mask register determines which status flags generate an interrupt by
setting the corresponding bit to 1.
Bit
Bit Name
reserved
Default
Access
Bit Description
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
stereo24_status cannot assert interrupt request
1 enables the FIFO PUSH error interrupt
1 enables the FIFO POP is empty interrupt
1 enables the FIFO POP is almost empty interrupt
1 enables the FIFO POP is half full interrupt
1 enables the FIFO POP is almost full interrupt
1 enables the FIFO POP is full interrupt
6
5
4
3
2
1
0
I2SIN_MASK_PUER
I2SIN_MASK_POE
I2SIN_MASK_POAE
I2SIN_MASK_POHF
I2SIN_MASK_POAF
I2SIN_MASK_POF
I2SIN_MASK_POER
0
0
0
0
0
0
0
1 enables the FIFO POP error interrupt
Table 45 I2S Input raw status register
Name
Base
AS3525_I2SIN_BASE
Raw status register
Default
0x00
I2SIN_RAW_STATUS
The read-only raw status register contains the actual bit values as reflected by the
FIFO controller status signals. I2SIN_PUER and I2SIN_POER are static bits, since
FIFO controller gives the PUSH/POP error bit only for one clock. This means that
these two bits remain asserted until they are cleared in the I2SIN_CLEAR register.
All other bits change state depending on the underlying logic, i.e. state of FIFO
controller.
Offset: 0x0008
Bit
Bit Name
Default
Access
Bit Description
7
stereo24_status
0
R
Status of write interface for 24 bit stereo mode
0: left audio sample will be transferred next
1: right audio sample will be transferred next
1 if FIFO PUSH error
1 if FIFO POP is empty
1 if FIFO POP is almost empty
1 if FIFO POP is half full
1 if FIFO POP is almost full
1 if FIFO POP is full
1 if FIFO POP error
6
5
4
3
2
1
0
I2SIN_PUER
I2SIN_POE
I2SIN_POAE
I2SIN_POHF
I2SIN_POAF
I2SIN_POF
0
0
0
0
0
0
0
R
R
R
R
R
R
R
I2SIN_POER
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