AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.8.1 I2S Input Register Mapping
I2S Input Interface Registers
Table 42 I2S Input Interface Registers
Register Name
I2SIN_CONTROL
I2SIN_MASK
Base Address
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
AS3525_I2SIN_BASE
Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Note
Control register
Interrupt mask register
Raw status register
Status register
I2SIN_RAW_STATUS
I2SIN_STATUS
I2SIN_CLEAR
Interrupt clear register
Audio data register
I2SIN_DATA
I2SIN_SPDIF_STATUS
SPDIF status signals register
Table 43 I2S Input Control Register
Name
Base
AS3525_I2SIN_BASE
Control register
12 bit wide read/write register containing the control bits of the I2SINIF.
Default
I2SIN_CONTROL
0x04
Offset: 0x0000
Bit
11
Bit Name
DMA_req_en
Default
Access
Bit Description
0
0
R/W
DMA request enable
0: disable
1: enable
10
mclk_invert
R/W
R/W
Invert MCLK
0: disable (SCLK changes at MCLK’s falling edge)
1: enable (SCLK changes at MCLK’s rising edge)
Define the source of SCLK and LRCK for I2SINIF
00: SCLK and LRCK from I2SOUTIF (used if AFE sends data)
01: SCLK and LRCK from external ADC device (outside AS3525)
10: SCLK and LRCK from SPDIF converter
11: SCLK and LRCK from I2SINIF’s clock controller
Define the source of SDATA for I2SINIF
00: SDATA from AFE
01: SDATA from external ADC device (outside AS3525)
10: SDATA from SPDIF converter
11: loopback SDATA from I2SOUTIF (test purpose)
0: ADC data from FIFO transferred in two 32-bit words to
I2SIN_DATA (first left and then right data as indicated by the
stereo24_status bit)
9,8
i2s_clk_source
00
00
0
7,6
sdata_source
14bit_mode
sclk_idle
R/W
R/W
R/W
5
1: ADC data from FIFO transferred in one 32-bit word to
I2SIN_DATA
Enable/disable SCLK for I2SINIF
4
0
0: SCLK enabled
1: SCLK disabled
3
SDATA_valid
sclk_edge
osr
0
R/W
R/W
R/W
0: SDATA ignored at first SCLK edge (I2S standard)
1: valid SDATA at first SCLK edge
0: data valid at negative edge of SCLK
1: data valid at positive edge of SCLK
Oversampling rate (needed for generating sclk and lrck)
00: 128x
2
1
1,0
00
01: 256x
10: 512x
11: 128x
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