AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.7 I2CMSI - I2C master/slave interface
This is a general control interface for chip-to-chip communication. The corresponding IOs are either used by the general purpose port C (xpc[6:7])
or by this I2C interface.
The features of this interface block are:
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serial 2-wire I2C bus master
supports standard (100 kbps) and fast speed (400kbps)
supports multi-master system architecture
programmable clock divider
programmable transfer count
programmable slave wait enable (for slave mode of operation, insertion of wait on the bus)
soft reset bit
interrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received)
status register
test register
Figure 24: I2C Interface
Table 41 I2C Interface Registers
Register Name
I2C1_DATA
Base Address
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
AS3525_I2C_MS_BASE
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
0x50
0x54
0x58
Note
transmit/receive FIFO data register
slave ID register 0
I2C1_SLAD0
I2C1_SLAD1
I2C1_CNTRL
I2C1_DACNT
I2C1_SEAD0
I2C1_SEAD1
I2C1_CPSR0
I2C1_CPSR1
I2C1_IMR
slave ID register 1
control register
master data count register
self ID of slave 0
self ID of slave 1
clock prescale register 0
clock prescale register 1
interrupt mask register
I2C1_RIS
raw interrupt status register
masked interrupt status register
I2C status register
I2C1_MIS
I2C1_SR
I2C1_TXCNT
I2C1_RXCNT
I2C1_TX_FLUSH
I2C1_INT_CLR
I2C1_TESTIN
I2C1_TESTOUT1
I2C1_TESTOUT2
transmit Fifo data count register
receive Fifo data count register
TX Fifo flush register
interrupt clear register
test register (monitors state of SCL and SDA)
test mode register for driving output interrupt
test mode register for driving SCLout, SCLOEn,
SDAOUT and SDAOEN signals
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