AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.8 I2SIN - I2S input interface
The I2S input interface module (called I2SINIF module hereafter) is used to connect an external audio source to the processor system. The
communication is based on the standardized I2S interface. The interface module connects to the processor system using the AMBA APB bus.
All the input left & right channel data are mapped to either 14 or 24 bit format, selectable within the control register. If the data word length is less
than 24 bit, the unused lower bits are set to zero. To reduce the interrupt frequency for the processor, a FIFO buffer is provided. The buffer can hold
up to 32 words of 48 bit length (left plus right channel).
Generation of interrupt request signal with several maskable interrupt sources (Pop Full, Pop Empty, Pop Error, Push Error, …etc)
The I2SINIF provides the following features:
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two independent clock domains: AMBA APB clock PCLK, I2S input clock i2si_sclk
FIFO (32 words/48 bit) separating clock domains
support of several oversampling rates: 128x, 256x, 512x
interrupt support for FIFO data read
DMA support for FIFO data transfer
The I2SINIF provides five different modes:
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input from on-chip audio ADC
input from external audio ADC in master mode (SCLK, LRCK generated by external ADC)
input from external audio ADC in slave mode (SCLK, LRCK, MCLK generated internally and fed to external ADC)
input from SPDIF (SPDIF to I2S converter)
feedback mode with input from I2S output interface: used for test purposes
Figure 25 I2S Input Interface
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