AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.6 I2cAudMas - I2C audio master interface
This is the control interface between the digital and the audio-part. The corresponding signal lines are connected inside of the MCM on the BGA
substrate. For test purposes of the audio chip only, the signals are available at dedicated balls.
•
•
•
•
•
•
•
•
•
•
•
The key features of this interface block are:
serial 2-wire I2C bus master
supports standard (100 kbps) and fast speed (400kbps)
7-bit addressing
sub-addressing
programmable clock divider
programmable transfer count
soft reset bit
interrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received)
status register
test register
Figure 23 I2C Audio Master Interface Block Diagram
Table 40 I2C Audio Master Registers
Register Name
I2C2_DATA
Base Address
Offset
0x00
0x04
0x0C
0x10
0x1C
0x20
0x24
0x28
0x2C
0x30
0x40
0x44
0x50
0x54
0x58
Note
transmit/receive FIFO data register
slave ID register
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
AS3525_I2C_AUDIO_BASE
I2C2_SLAD0
I2C2_CNTRL
I2C2_DACNT
I2C2_CPSR0
I2C2_CPSR1
I2C2_IMR
control register
master data count register
clock prescale register 0
clock prescale register 1
interrupt mask register
I2C2_RIS
raw interrupt status register
masked interrupt status register
I2C status register
I2C2_MIS
I2C2_SR
I2C2_INT_CLR
I2C2_SADDR
I2C2_TESTIN
I2C2_TESTOUT1
I2C2_TESTOUT2
interrupt clear register
sub-address register
test register (monitors state of SCL and SDA)
test mode register for driving output interrupt
test mode register for driving SCLout,
SCLOEn, SDAOUT and SDAOEN signals
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com Revision 1.13
57 - 194
AMSCO [ AMS(艾迈斯) ]
