AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.15 CCU - Chip Control Unit
Following chapters describe the functions of the CCU.
Table 88 CCU Registers
Register Name
CCU_SRC
Base Address
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
AS3525_CCU_BASE
Offset
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
Note
Software reset control register
CCU_SRL
Software reset lock register
Memory map register
CCU_MEMMAP
CCU_IO
IO configuration register
System configuration register
Chip version register
CCU_SCON
CCU_VERS
CCU_SPARE1
CCU_SPARE2
spare register 1 (for future use)
spare register 2 (for future use)
7.3.15.1 Reset Controller
•
Generation of the internal reset: the external reset pin XRES is used to generate the internal global reset. This internal reset is synchronised
to clk_main and the active reset time is enlarged. This is necessary to wait for the startup of the DC/DC converter and LDO's that are
generating the supplies of the digital chip. The time assumed for this startup is 10 ms, therefore 2^18 cycles of clk_main are counted before
the internal reset is released. This mechanism is also used for the WATCHDOG reset.
•
Softreset: for each module, the reset can also be generated by SW control. For this purpose, the SW can write to the software reset control
register (CCU_SRC). To avoid unintended SW resets, the access to this control register is locked by the SW reset lock register (CCU_SRL).
So the correct usage is:
•
•
•
write CCU_SRC
write CCU_SRL (magic number 0x1A720212) to CCU_LOCK to activate resets
write CCU_SRL (0x00000000) to deactivate resets
Table 89 Software Reset Control Register
Name
Base
Default
0x00
CCU_SRC
AS3525_CCU_BASE
Software Reset Control Register
Offset: 0x0000h
Writing a logic 1 to the single bits in the read/write register enables resets to each
module.
Bit
24
Bit Name
Default
Access
Bit Description
DBOP_EN
0
0
0
0
0
0
0
0
R/W
1: enable DBOP reset
0: disable DBOP reset
23
22
21
20
19
18
17
MBIST_EN
SPDIF_EN
TIMER_EN
SSP_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1: enable MBIST manager reset
0: disable MBIST manager reset
1: enable SPDIF reset
0: disable SPDIF reset
1: enable timer module reset
0: disable timer module reset
1: enable synchronous serial port reset
0: disable synchronous serial port reset
1: enable watchdog timer module reset
0: disable watchdog timer module reset
1: enable compact flash/IDE reset (except AHB part)
0: disable compact flash/IDE reset (except AHB part)
1: enable compact flash/IDE’s AHB interface reset
0: disable compact flash/IDE’s AHB interface reset
WDO_EN
IDE_EN
IDE_AHB_EN
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com Revision 1.13
114 - 194
AMSCO [ AMS(艾迈斯) ]
