F I N A L
PACKAGE THERMAL SPECIFICATIONS
TJ = TCASE + P • θJC
TA = TJ – P • θJA
TCASE = TA + P • [θJA – θJC
The Am386SX/SXL/SXLV processors are specified for
operation when TCASE (the case temperature) is within
the range of 0°C to +100°C for commercial parts, and
–40°C to +100°C for industrial parts. TCASE can be mea-
sured in any environment to determine whether the
Am386SX/SXL/SXLV processors are within the speci-
fied operating range. The case temperature should be
measured at the center of the top surface opposite the
pins.
]
where:
TJ, TA, TCASE = Junction, Ambient, and Case Temperature
θJC, θJA
= Junction-to-Case and Junction-to-Ambient
Thermal Resistance, respectively
P
= Maximum Power Consumption
The ambient temperature (TA) is guaranteed as long as
In the 100-lead PQFP package, θJA=45.0 and θJC=11.0.
T
is not violated. The ambient temperature can be
CASE
calculated from θJC and θJA and from these equations:
ELECTRICAL SPECIFICATIONS
The Am386SX/SXL/SXLV CPU has modest power re-
quirements. However, its high clock frequency and 47
output buffers (address, data, control, and HLDA) can
cause power surges as multiple output buffers drive
new signal levels simultaneously. For clean on-chip
PEREQ input has an internal pull-down resistor of ap-
proximately 20 Kohms, built into the Am386SX/SXL/
SXLV CPU to keep these signals inactive when a
387SX-compatible math coprocessor is not present in
the system (or temporarily removed from its socket).
power distribution at high frequency, 14 V
and
CC
In typical designs, the external pull-up resistors shown
in Table 1 are recommended. However, a particular de-
sign may have reason to adjust the resistor values rec-
ommended here, or alter the use of pull-up resistors in
other ways.
18 V
pins separately feed functional units of the
SS
Am386SX/SXL/SXLV CPU.
Power and ground connections must be made to all ex-
ternal V and V pins of the Am386SX/SXL/SXLV
CC
SS
CPU. On the circuit board, all V pins should be con-
CC
Other Connection Recommendations
nected on a V
plane, and V pins should be con-
CC
SS
nected on a GND plane.
For reliable operation, always connect unused inputs to
an appropriate signal level. NC pins should always re-
Power Decoupling Recommendations
main unconnected. Connection of NC pins to V
or
CC
Liberal decoupling capacitors should be placed near
the Am386SX/SXL/SXLV CPU. The Am386SX/SXL/
SXLV CPU driving its 24-bit address bus and 16-bit
data bus at high frequencies can cause transient power
surges, particularly when driving large capacitive
loads. Low inductance capacitors and interconnects
are recommended for best high frequency electrical
performance. Inductance can be reduced by shorten-
ing circuit board traces between the Am386SX/SXL/
SXLV CPU and decoupling capacitors as much as pos-
sible.
V
will result in component malfunction or incompati-
SS
bility with future steppings of the Am386SX/SXL/SXLV
CPU.
Particularly when not using the interrupts or bus hold
(as when first prototyping), prevent any chance of spu-
rious activity by connecting these associated inputs to
GND:
Pin
40
38
4
Signal
INTR
NMI
HOLD
Resistor Recommendations
If not using address pipelining, connect pin 6 (NA)
through a pull-up in the range of 20 Kohms to V
The ERROR, FLT, and BUSY inputs have internal pull-
up resistors of approximately 20 Kohms, and the
.
CC
Table 1. Recommended Resistor Pull-Ups to V
CC
Pin
Signal
Pull-Up Value
Purpose
Lightly pull ADS inactive during Am386SX/SXL/SXLV
CPU Hold Acknowledge states.
16
ADS
20 Kohms ± 10%
Lightly pull LOCK inactive during Am386SX/SXL/
SXLV CPU Hold Acknowledge states.
26
LOCK
20 Kohms ± 10%
Am386SX/SXL/SXLV Microprocessors Data Sheet
29
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