F I N A L
nom + 9
nom + 6
nom + 3
Output Valid Delay (ns)
nom
nom –3
50
75
100
125
150
CL (picofarads)
Note:
This graph will not be linear outside the CL range shown.
15021B–081
Figure 20. Typical Output Valid Delay Versus Load Capacitance
at Maximum Operating Temperature (CL=50 pF)
8
6
Rise Time (ns)
0.8 V – 2.0 V
4
2
8
50
75
100
125
150
CL (picofarads)
15021B–082
Note:
This graph will not be linear outside the CL range shown.
Figure 21. Typical Output Rise Time Versus Load Capacitance
at Maximum Operating Temperature
Am386SX/SXL/SXLV Microprocessors Data Sheet
27