F I N A L
Internal Initialization
Reset
Cycle 1
≥ 15 CLK2 duration if not
going to request self-test.
≥ 80 CLK2 duration before
requesting self-test.
Non-Pipelined
(Read)
If self-test is performed, add
(220) + 60* to these numbers.
T1
T2
*
*
*
*
1
2
3
17 18 19 395 396 397 398
CLK2
Reset
*
Approximately
φ
φ
φ
φ
φ
φ
φ
φ
φ
1 2
1
1
2
1
2
2
2
CLK (Internal)
Negated to allow sensing of a
387DX math coprocessor
No self-test
BUSY
(Note 1)
Low to begin self-test (Note 2)
Asserted to indicate 387DX
math coprocessor protocol
ERROR
Up to 30 CLK2
Up to 30 CLK2
BHE, BLE, W/R,
M/IO, HLDA
Valid 1
Valid 1
Low
During Reset
A23–A1,
D/C, LOCK
High During Reset
High During Reset
Up to 30 CLK2
ADS
NA
READY
D15–D0
(Floating)
SMI
Notes:
1. BUSY should be held stable for eight CLK2 periods before and after the CLK2 period in which the RESET falling edge
occurs.
2. If self-test is requested, the Am386SXLV microprocessor outputs remain in their reset state as shown here.
16305C–009
Figure 11. Bus Activity from Reset Until First Code Fetch (Am386SXLV Only)
22
Am386SX/SXL/SXLV Microprocessors Data Sheet
AMD [ AMD ]
