F I N A L
DIFFERENCES BETWEEN THE Am386SX/SXL/SXLV AND Am386DX/DXL CPU
The following are the major differences between the
Am386SX/SXL/SXLV and the Am386DX/DXL CPU.
For brevity, throughout this section the Am386SX/SXL/
SXLV CPU is referred to as the SX CPU, and the
Am386DX/DXL CPU is referred to as the DX CPU.
■ The DX CPU uses A31 and M/IO as selects for the
math coprocessor. The SX CPU uses A23 and M/IO
as selects.
■ The DX CPU prefetch unit fetches code in four-byte
units. The SX CPU prefetch unit reads two bytes as
one unit (like the 80286). In BS16 mode, the DX
CPU takes two consecutive bus cycles to complete
a prefetch request. If there is a data read or write re-
quest after the prefetch starts, the DX CPU will fetch
all four bytes before addressing the new request.
■ The SX CPU generates byte selects on BHE and
BLE (like the 8086 and 80286) to distinguish the
upper and lower bytes on its 16-bit data bus. The
DX CPU uses four byte selects, BE3–BE0, to distin-
guish between the different bytes on its 32-bit bus.
■ Both the DX CPU and SX CPU have the same log-
ical address space. The only difference is that the
DX CPU has a 32-bit physical address space and
the SX CPU has a 24-bit physical address space.
The SX CPU has a physical memory address space
of up to 16 Mbyte instead of the 4 Gbyte available
to the DX CPU. Therefore, in SX CPU systems, the
operating system must be aware of this physical
memory limit and should allocate memory for appli-
cations programs within this limit. If a DX CPU sys-
tem uses only the lower 16 Mbyte of physical
address, then there will be no extra effort required
to migrate DX CPU software to the SX CPU. Any
application which uses more than 16 Mbyte of
memory can run on the SX CPU, if the operating
system utilizes the SX CPU’s paging mechanism. In
spite of this difference in physical address space,
the SX CPU and the DX CPU can run the same op-
erating systems and applications within their re-
spective physical memory constraints.
■ The SX CPU has no bus sizing option. The DX CPU
can select between either a 32-bit bus or a 16-bit
bus by use of the BS16 input. The SX CPU has a
16-bit bus size.
■ The NA pin operation in the SX CPU is identical to
that of the NA pin on the DX CPU with one excep-
tion: the DX CPU NA pin cannot be activated on 16-
bit bus cycles (where BS16 is Low in the DX CPU
case), whereas NA can be activated on any SX
CPU bus cycle.
■ The contents of all SX CPU registers at reset are
identical to the contents of the DX CPU registers at
reset, except for the DX register. The DX register
contains a component-stepping identifier at reset,
that is:
– In the DX CPU, after reset:
DH = 3 indicates DX CPU
DI = revision number
– In the SX CPU, after reset:
DH = 23H indicates SX CPU
DL = revision number
■ The SX CPU has an input called FLT, which three-
states all bi-directional and output pins, including
HLDA, when asserted. It is used with ON-Circuit
Emulation (ONCE).
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Am386SX/SXL/SXLV Microprocessors Data Sheet
AMD [ AMD ]
