F I N A L
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
CLK2
FLT
Control
Valid
Valid
Valid
Data
Address
Reset
SMI
Valid
16306B–008
Figure 12. Entering and Exiting FLT (Am386SXLV Only)
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
φ 1
CLK2
SMI
SMM in progress
Drive released by CPU
System may initiate another
SMI when necessary*
SMIADS
CPU driving SMI
System control of SMI
*Once initiated, the system must hold SMI Low until the first SMIADS. At this time, the system cannot drive SMI until three
CLK2 cycles after the CPU drives SMI High. (The CPU will drive SMI High for two CLK2 cycles. The additional clock allows
the CPU to completely release SMI and prevents any driver overlap.)
16306B–011
Figure 13. Initiating and Exiting SMM (Am386SXLV Only)
φ 2
φ 2
SMM in progress
CLK2
SMI
CPU drives SMI High for two CLK2 cycles 6–8
clocks after RESET is asserted.
RESET
16306B–010
Figure 14. RESET and SMI (Am386SXLV Only)
Am386SX/SXL/SXLV Microprocessors Data Sheet
23
AMD [ AMD ]
