F I N A L
Th
Ti or T1
φ
φ
φ
φ
φ
2
1
2
1
2
CLK2
t9
t8
Min
Max
Min
Max
BHE, BLE,
LOCK
(High Z)
t10, t10s
Max
t11, t11s
Min
Min
Min
Min
Max
Max
W/R, M/IO, D/C,
ADS, SMIADS
(High Z)
t7
t6
Max
A23–A1
D15–D0
(High Z)
Min
t13
t12
Max
Min
Max
(High Z)
t14f
t32
t14
Min
Min
Max
Min
Max
HLDA
SMI
(High Z)
t31
Max
Min
Max
(High Z)
16305C–012
Figure 16. Output Float Delay Entering and Exiting FLT (Am386SXLV Only)
RESET
Initialization Sequence
φ
φ
φ
φ
φ
φ
1
2 or
1
2 or
1
2
CLK2
t26
RESET
t25
The second internal processor phase following RESET High-to-Low transition (provided t25 and t26 are met) is φ2.
15021B–084
Figure 17. RESET Setup and Hold Timing and Internal Phase
Am386SX/SXL/SXLV Microprocessors Data Sheet
25
AMD [ AMD ]
