F I N A L
Cycle 0
Cycle 1
Th
Cycle 2
Ti or T1
φ
φ
φ
φ
φ
2
1
2
1
2
CLK2
t9
t8
Min
Max
Min
Max
BHE, BLE,
LOCK
(High Z)
t10, t10s*
Max
t11, t11s*
Min
Min
Min
Min
Max
Max
W/R, M/IO, D/C,
ADS, SMIADS*
(High Z)
t7
t6
Max
A23–A1
D15–D0
(High Z)
Min
t13
t12
Max
Min
Max
(High Z)
t13—Also applies to data float when write
cycle is followed by read or idle
t14f
t14
Min
Max
Min
Max
HLDA
SMI*
Valid 0
Valid 1
Valid 2
Min
Max
t31
* – On Am386SXLV only
Figure 15. Output Float Delay and HLDA and SMI* Valid Delay Timing
24
Am386SX/SXL/SXLV Microprocessors Data Sheet