HPR17: HomePNA Status Control (Register 17)
Table 51. HPR17: HomePNA Status Control (Register 17)
Read/
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
Write
Reads will produce undefined results;
Writes = 0
15:13 Reserved
R/W
1 = Any1Home Link Packet Disable
0 = Any1Home Link Packet Enable
12
11:7
6
Any1home
R/W
R/W
R
0
Reads will produce undefined results;
Writes = 0
Reserved
1 = Last packet received was sent at high power
0 = Last packet received was sent at low power
Received_Power
0
1 = Last packet received was sent at high power
0 = Last packet received was sent at low power
5
Received_Speed
R
0
0
1 = Last packet received was sent at Version
XX
4
Received_Ver
Reserved
R
Reads will produce undefined results;
Writes = 0
3:0
R/W
HPR18 and HPR19: HomePNA PHY TxCOMM
(Registers 18 and 19)
Table 52. HPR18 and HPR19: HomePNA PHY TxCOMM (Registers 18 and 19)
Read/
Write
Default
Hex
Soft
Reset
Hex
Mnemonic
Description
The 32-bit preamble transmitted on the
HomePNA PHY. Register 12 contains the high
word and Register 13 the low word.
12-13
PHY_TX_COMM (4)
R/W
All 0s
All 0s
The 32-bit transmitted data field is to be used for out-
of-band communication between PHY management
entities. No protocol for out-of-band management has
been defined. Accessing the low word causes the PHY
to send all-0 PCOMs until the high word has been ac-
cessed. Once accessed, the next transmitted packet
will cause this register’s contents to be shifted out in
the PCOM field of the transmitted packet. Upon trans-
mission, this register will read back as all 0s. A non-null
transmitted PCOM will set the TxPCOM Ready bit in
the Event Status Register (Register HPR26). An ac-
cess to any of the two TxPCOM words will clear the Tx-
PCOM Ready bit in the ISTAT register.
Am79C978
183
AMD [ AMD ]
