HPR26: HomePNA PHY Event Status (Register 26)
Table 58. HPR26: HomePNA PHY Event Status (Register 26)
Read/
Write
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
PHY_Event Status
15:10 Reserved
R
R
0
0
0
0
Indicates a valid RxPCOM. An access to the
RxCOM MSB Register 21 will clear this bit.
9
8
RxPCOM
TxPCOM
Indicates a valid TxPCOM. Any access to the
TxCOM registers (Registers 18 and 19) will
clear this bit.
R
0
0
7:4
3
Reserved
Reads will produce undefined results.
Status is cleared by writing a 0.
Status is cleared by writing a 0.
R
Packet Received
Packet Transmitted
R/W
R/W
0
0
0
0
2
A valid remote command was received.
Status is cleared by writing a 0.
1
0
Remote Command Received
Remote Command Sent
R/W
R/W
0
0
0
0
A remote command has been sent.
Status is cleared by writing a 0.
HPR27: HomePNA PHY Event Status (Register 27)
The Event Status register reports the state of each
event source. Any bit may be written and so facilitate
software-stimulated event testing.
Table 59. HPR27: HomePNA PHY Event Status (Register 27)
Read/
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
Write
AID_CTRL
This value defines the number of TCLKs (116.6
ns) separating AID symbols.
15:8
7:0
AID_INTERVAL
AID_ISBI
R/W
R/W
14
40
14
40
This value defines the number of TCLKs (116.6
ns) separating AID symbol 0.
HPR28: HomePNA PHY ISBI Control (Register 28)
Table 60. HPR8: HomePNA PHY ISBI Control (Register 28)
Read/
Write
Default
Hex
Soft
Reset
Bits
Mnemonic
ISBI_CTRL
Description
This value defines the number of TCLKs (116.6
ns) separating data pulses for Symbol 0 in low
speed mode.
15:8
7:0
ISBI_SLOW
ISBI_FAST
R/W
R/W
2C
1C
2C
1C
This value defines the number of TCLKs (116.6
ns) separating data pulses for Symbol 0 in high
speed mode.
186
Am79C978
AMD [ AMD ]
