HPR24: HomePNA PHY Noise Control 2 (Register
24)
Table 56. HPR24: HomePNA PHY Noise Control 2 (Register 24)
Read/
Write
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
PHY_NOISE_CTRL2
Sets the attack characteristics of the NOISE
algorithm. High nibble sets number of noise
events needed to raise the NOISE level
immediately, while the low nibble is the number
of noise events needed to raise the level at the
end of an 870 ms period.
15:8
7:0
Noise Attack
R/W
R
F4
F4
Reserved
Reads will produce undefined results
HPR25: HomePNA PHY Noise Statistics (Register
25)
Table 57. HPR25: HomePNA PHY Noise Statistics (Register 25)
Read/
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
Write
PHY_NOISE_STAT
This is the digital value of the
SLICE_LVL_NOISE output. It is effectively a
measure of the noise level on the wire and
tracks noise by counting the number of false
triggers of the NOISE comparator in an 800 ms
window. When auto-adaptation is enabled (bit 5
of the PHY_Control Register is false), this
register is updated with the current NOISE
count every 50 ns. When adaptation is
disabled, this register may be written to and is
used to generate both the SLICE_LVL_NOISE
and SLICE_LVL_DATA signals.
15:8
Noise Level
R/W
R/W
03
FF
03
FF
This is a measurement of the peak level of the
last valid (non-collision) AID received.
7:0
Peak Level
Am79C978
185
AMD [ AMD ]
